3
Total investments
0
Early stage
1
Mid stage
0
Late stage
24y
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2 investments ยท sorted by recency
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Board Member
May 2012
ASELTA operates in the IC manufacturing world, and provides advanced software solutions for wafer and mask patterning based on e-Beam technology. ASELTA is enabling the use of e-Beam lithography equipment for all advanced technology nodes such as 7nm and beyond.
Investor and Board Member
Jan 2002
Upgrade Your Design and Verification with Jasper!
Jasper Design Automation's mission is to make full formal IC verification a competitive advantage for its customers. Jasper's formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid post-silicon validation and debug.
Experience ยท 6 entries
All (6)
Investments (3)
Founder (2)
Board (3)
2012
Board Member
May 2012
ASELTA operates in the IC manufacturing world, and provides advanced software solutions for wafer and mask patterning based on e-Beam technology. ASELTA is enabling the use of e-Beam lithography equipment for all advanced technology nodes such as 7nm and beyond.
2010
Managing Director
Jun 2010
Harvest Management Partners is a boutique investment bank and advisory services company that specializes in helping technology companies harness their value and distribute it to their shareholders. Harvest Management Partners main focus is on software, security/cybersecurity, semiconductor (SIP / AI / Photonics), EDA, PLM), AR/VR, automotive technology and services. We typically advise privately held companies on projects ranging from overall strategy to market focus and ultimately M&A. Our passion is your success!
2002
T
Tera Systems
Board Member & CEO
Jul 2002
Investor and Board Member
Jan 2002
Upgrade Your Design and Verification with Jasper!
Jasper Design Automation's mission is to make full formal IC verification a competitive advantage for its customers. Jasper's formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid post-silicon validation and debug.
1998
S
Sequence Design
Founder & CEO
Jan 1998
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Investment activity
2002โ2012 ยท 3 investments
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