The verification of electrical errors at chip-level has always been the missing step in chip design closure – even though a chip is, basically, a very large circuit. The complexity of such an analysis has so far made it impossible.
Consequently, considerable effort is made throughout the design processes to avoid electrical errors from occurring in the first place. Experience, however, shows that without a verification solution dedicated to the analysis of electrical circuits at the chip scale, some errors elude the vigilance of design engineers, even with the most comprehensive design flows.
Those errors have severe consequences, ranging from delays in the project schedule (thus increasing its cost), failed time-to-market and in the worst case, product recalls (and the major financial impact as well as brand image impact this can imply).
Aniah has developed a radically new algorithm that enables an electrically accurate, full-chip analysis at transistor-level.
It introduces a new paradigm for verification with a tool that is both intuitive and comprehensive, delivering on its promise of a full coverage of electrical errors.
